The present invention relates to a semiconductor structure including backside dummy plugs in a substrate and methods of manufacturing the same.
3D integration, or chip stacking, refers to a method of assembling two or more semiconductor chips so that the semiconductor chips that are placed in physical proximity to one another are also electrically connected among one another. 3D integration is typically performed vertically, i.e., one chip is placed above or below another chip. When two chips are brought together vertically, a set of conductive contact structures on the top surface of an underlying chip is aligned to another set of conductive contact structures on the bottom surface of an overlying chip. The conductive structures may be formed on the side of metal interconnect structures, or they may be formed on the side of a substrate on which semiconductor devices are formed.
3D integration may be performed between a pair of substrates, a substrate and a set of chips, or between multiple pairs of chips. 3D integration provides vertical signal paths between stacked chips, providing a wide bandwidth for transmitting and receiving electrical signals between stacked chips. The vertical signal paths are effected by through-substrate vias (TSVs), which are vias extending at least from a topmost surface of a semiconductor device layer in a substrate to a backside surface of the substrate. 3D integration effectively reduces the lengths of signal paths and allows faster transmission of electrical signals between various device components located in various portions of stacked semiconductor chips.
Limitations to the benefits of 3D integration are imposed by secondary effects of TSVs. Such limitations are caused, for example, by inter-wafer thermal conductivity, cross-talk between signals in TSVs, and structural reliability of TSVs throughout the operational lifetime of the stacked structure. These limitations to 3D integration can degrade the overall system level performance of a stacked structure of multiple semiconductor chips.
Addressing such challenges without sacrificing performance of semiconductor chips in the system can be difficult. For example, in order to enhance inter-wafer thermal conductivity to provide sufficient cooling of power-consuming chips (such as processor chips), it is desirable to have a large number of uniformly distributed TSV. However, formation of a large number of TSVs requires use of a large chip area for TSVs, thereby reducing the chip area available for use as active areas, i.e., areas in which semiconductor devices can be built. Increasing the number of TSVs has the effect of reducing the active areas or increasing the overall chip size, and may not be a viable solution in many instances.
As far as reduction of signal cross-talk is concerned, it is desirable to provide shielding structures that laterally surround TSVs to minimize signal couplings among electrical signals through the TSVs. However, formation of such shielding structures requires large active areas, rendering such an option practically unaffordable.
As far as enhancement of thermal reliability of the stacked chip structure is concerned, the mismatch between the coefficient of thermal expansion (CTE) of a semiconductor material in a semiconductor chip and the CTE of embedded conductive material that constitute the TSVs generate mechanical stress during temperature cycling at any subsequent high-temperature processing steps, including thermocompression bonding steps, and during high-temperature operation of the stacked chip structure. Accumulation of stress in the TSVs can cause cracking in the stacked chip structure resulting in a structural reliability problem such as dislodging of some of the TSV and subsequently vertical movement of the TSVs within a semiconductor chip.